This invention relates to III-IV compound semiconductor devices implemented in planar processing to form complementary transistor logic structures. More particularly, this invention relates to the combination of a p-MODFET structure combined wit an enhancement mode n-channel heterojunction FET.
Gallium arsenide field effect transistors are rapidly emerging as a serious competitor to the more mature silicon microelectronic technologies, especially in the areas of low power logic circuits. Gallium arsenide is especially attractive because of the very high electron mobility compared to that found in silicon. Unfortunately, the hole mobility in gallium arsenide is similar to that found for holes in silicon. Therefore the design of complementary gallium arsenide logic circuits suffers in speed due to this low hole mobility. The low value of hole mobility results in low p-channel transconductance which produces low switching speeds. The p-channel transconductance obtained in complementary circuits based on gallium arsenide JFETs is only five mS/mm compared to about fifty to one hundred mS/mm for the n-channel transconductance.
It has recently been demonstrated that the mobility of holes can be drastically improved by the use of a p-(Al,Ga) As/i-GaAs modulation doped heterostructure. The mobilities of holes in these structures at moderately low temperatures are comparable to those of electrons in bulk gallium arsenide MESFET's. Such p-MODFET structures have yet to be successfully combined with a complementary n-channel structure in terms of a planar technology which can reliably produce complementary gallium arsenide logic devices having uniform voltage thresholds and reliable operating characteristics.